PURPOSE: To reduce number of RAMs to be employed and to simplify write/read control.

CONSTITUTION: This conversion circuit is provided with a dual port RAM 1 having plural input ports and data output ports, writing serial data with a 1st write control signal and reading the data with a 1st read control signal with a delay of an optional bit length from the 1st write control signal, a dual port RAM 2 writing required part of data read from the dual port RAM 1 with a 2nd write control signal and then reading a parallel data signal with a 2nd read control signal, a signal generating means 3 receiving a 1st reference clock and a reference signal and outputting sequentially the 1st write control signal, the 1st read control signal and the 2nd write control signal and a signal generating means 4 receiving the reference frame signal and the 2nd reference clock and outputting the 2nd read control signal.