PURPOSE: To decrease the number of circuit element and to reduce the circuit scale of a serial/parallel conversion circuit.

CONSTITUTION: The n-stage shift registers 23 and 24 successively shift the input signals by a master clock. The selectors 21 and 22 select the input signal in place of the n-i stage outputs of the registers 23 and 23 in a (i0<i<n)-bit parallel output mode and input these signals to the (n-i+1) stage of the registers 23 and 24. A latch circuit 35 latches and outputs the outputs of each stage of the registers 23 and 24 by the clocks obtained by dividing the master clock.