To halve a frequency of a basic clock pulse to be applied for drive at the same data rate by detecting a rising edge of the basic clock pulse and a rising edge of an inverted pulse respectively.

From a parallel data input terminal 1, n-bit data are received at a data rate fbps. A circuit 7 generates an in-phase byte clock pulse Byte Clock 0 and an inverted byte clock pulse Byte Clock 1 from the basic clock pulse of a frequency f/2Hz and gives them to byte clock pulse input terminals 2a, 2b. An OR circuit 9 receives outputs (1), (2) of edge detection circuits 8a, 8b and its output (3) acts like a byte clock pulse of a frequency fHz. An input section 3 is driven by the byte clock pulse (3), a multiplexer 4 is driven by a PLL synthesizer 5 and provides an output of serial data at a data rate of n.fbps.