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Patent Searching and Data

Document Type and Number:
Japanese Patent JPH10135838
Kind Code:

To compose a CMI/NRZ conversion circuit of a digital circuit without using a phase locked loop circuit by converting a holding signal holding from the changing point of CMI(code mark inversion) code data at a middle point to the next middle point to NRZ(non-return to zero) code data with the period of a transfer clock.

A falling detection part 1, counter 2 and a decoder 3 constituting a middle point detecting circuit detect the middle point of transferring clocks generated from CMI code data to detect the changing point of CMI code data at this detected middle point. A flip-flop 4 as a holding signal generating circuit generates a holding signal from this data changing point to a point before the next middle point. A flip-flop 6 as a conversion circuit receives a holding circuit from the flip-flop 4 and converts it to NRZ code data with the period of a transferring clock to output. Then a CMI/NRZ conversion circuit is realized by the digital circuit.

Sakaguchi, Taiichiro
Nagusa, Yasutsugu
Ueno, Noriyuki
Moriwake, Masaru
Onodera, Takashi
Application Number:
Publication Date:
May 22, 1998
Filing Date:
October 30, 1996
Export Citation:
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International Classes:
H03M5/12; H04L25/40; H04L25/49; (IPC1-7): H03M5/12; H04L25/40; H04L25/49
Attorney, Agent or Firm:
茂泉 修司