PURPOSE: To prevent data from being destroyed owing to the overlap of an output by delaying a start signal for a precedent-stage IC for parallel/serial conversion and thus obtaining a start signal for a cascaded trailing-stage IC.

CONSTITUTION: The precedent-stage IC1 for parallel/serial conversion which increases processing data capacity starts with the start signal 1 from a CPU 3 to convert parallel data P1 into serial data S1. The trailing-stage IC 2 similar to the IC 1 starts with the start signal 2 which is a delay time τ1 delayed behind the signal 1 to convert parallel data P2 into serial data S2, and the serial data S consisting of the data S1 and S2 is supplied to the CPU 3 through the IC 1. Thus, the start signal is delayed, so even if response characteristics of the ICs 1 and 2 to the start signals vary, the signals S1 and S2 continue, but a space τ2 is generated, thereby preventing the data from being destroyed owing to their mutual overlap.