PURPOSE: To accelerate data output speed by increasing the operation frequency of an FIFO memory, and to obtain a means, in which the area of a chip is reduced by preventing addressing at every bit.

CONSTITUTION: Series input data are stored temporarily in a write frame 30 having the fixed width of (n) bit width, and all (n) bit width frames are written in parallel to a RAM array 22 at a time. Parallel data from the RAM array 22 are stored temporarily in a read frame 40, and transmitted in series to an FIFO output 53. Consequently, since the number of required pointers is reduced, the size of the whole chip is scaled down. Data written to an FIFO can be utilized instantaneously by coupling the read frame 40 with the write frame 30 and the above-mentioned series input data, and the read frame 40 can receive backfilled data from the write frame 30.