PURPOSE: To devise a circuit such that one clock generating circuit is enough to give a clock signal to plural converters and to obtain a clock signal fed to the plural converters even when at least one video signal among plural video signals fed respectively to the plural converters is present thereon.

CONSTITUTION: The system is provided with plural converters AD1, AD2,...,ADN receiving a video signal respectively, an input signal selection circuit 1 using a priority table receiving the plural video signals in common and a clock generating circuit CK receiving the video signal selected by the selective circuit 1 and generating the clock signal based on the synchronizing signal and the clock generating circuit CK gives the clock signal to the plural converters AD1, AD2,...,ADN in common.