Title:
SERIAL/PARALLEL CONVERTER
Document Type and Number:
Japanese Patent JP2565144
Kind Code:
B2
Abstract:
PURPOSE: To provide a high-speed, highly integrated and low-power serial/ parallel converter capable of being used as a bidirectional shift register as well by transferring data based on a second clock whose phase is opposite to a first clock.
CONSTITUTION: This converter is provided with plural holding circuits 5-9 for inputting the serial data signals of one system and a shift register 4 composed of first and second clocked inverters for outputting the holding control signals of the holding circuits 5-9. One of the optional holding circuits for holding time sequentially adjacent serial data signals among the serial data signals makes the output of the first clocked inverter for transferring the data based on the first clock the holding control signal. The other holding circuit inputs the output from the first clocked inverter and means the output of the first clocked inverter for transferring the data based on the second clock whose phase is opposite to the first clock the holding control signal. Thus, the number of the components of the shift register is reduced to a half and a low-power and high-speed operation is performed.
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Inventors:
SAKURAI YOICHI
Application Number:
JP30353194A
Publication Date:
December 18, 1996
Filing Date:
December 07, 1994
Export Citation:
Assignee:
SEIKO EPSON CORP
International Classes:
H03M9/00; (IPC1-7): H03M9/00
Domestic Patent References:
| JP5161760A |
Attorney, Agent or Firm:
Kisaburo Suzuki (1 outside)