Title:
A/D CONVERTER
Document Type and Number:
Japanese Patent JP3059263
Kind Code:
B2
Abstract:
PURPOSE: To facilitate zero offset adjustment without varying a ladder resistance by outputting an optional offset voltage or a low potential side power supply voltage to a 2nd capacitor when a reference voltage or an analog input voltage is inputted to a chopper type comparator.
CONSTITUTION: A ladder resistor 1 is formed by connecting lots of resistors R of the same resistance value and a zero offset resistor R/2 in series. One of reference voltages between terminals of the resistor 1 and an analog input voltage are compared by a chopper type comparator 4 via a 1st capacitor C1. A voltage application circuit 7 is connected to the comparator 4 via a 2nd capacitor C2 and when a reference voltage is inputted to the comparator 4, a prescribed offset voltage is outputted to the capacitor C2. Moreover, when an analog input voltage is inputted, a low potential side power supply voltage Vss is outputted to the capacitor C2. As a result, the reference voltage inputted to the comparator 4 based on the capacitance of the capacitor C2 is offset and when the capacitance of the capacitor C2 is changed, the offset quantity is adjusted without changing a current flowing to the resistor 1.
Inventors:
Keizo Inukai
Application Number:
JP27143291A
Publication Date:
July 04, 2000
Filing Date:
October 18, 1991
Export Citation:
Assignee:
富士通株式会社
富士通ヴィエルエスアイ株式会社
富士通ヴィエルエスアイ株式会社
International Classes:
H03M1/10; H03M1/38; (IPC1-7): H03M1/10; H03M1/38
Domestic Patent References:
| JP297123A | ||||
| JP59111414A |
Attorney, Agent or Firm:
Hironobu Onda