PURPOSE: To prevent the degradation in the accuracy of a reception data by converting a clock into a parallel signal with a tapped shift register to obtain a mask data and using the mask data to clear the invalid data bit of an input data subjected to serial/parallel conversion to zero.

CONSTITUTION: A 1st tapped shift register 1 using a 1st input clock representing the bit shift timing of a serial input data as a shift clock and converting a serial form input data into a parallel form, a 2nd tapped shift register 2 receiving a 2nd input clock representing the sampling unit of a serial form input data as the input, using a 1st input clock as a shift clock and converting a 2nd input clock into a parallel form are provided. Then the inversion of the MSB of the output of the shift register 2 and output bits are exclusively ORed to obtain a mask data, it is ANDed with the output data of the shift register 1, thereby clearing an invalid data to zero. Thus, the degradation in the accuracy of a reception data is prevented.