Title:
A/D CONVERTER
Document Type and Number:
Japanese Patent JPH04255113
Kind Code:
A
Abstract:
PURPOSE: To obtain a stable data by adding a simple circuit to the A/D converter so as to prevent production of an error in an A/D conversion data due to noise.
CONSTITUTION: A frequency of a clock pulse led from a clock pulse generating circuit 1 is multiplied by a frequency multiple circuit 3 as a multiple of an integral number and after an A/D converter 2 is in sampling operation by using a clock pulse whose frequency is increased, plural converted digital outputs are averaged by a signal averaging circuit 4 based on a clock pulse with the initial frequency an the averaged digital signal is outputted as an A/D conversion data.
Inventors:
KISHIDA OSAMU
Application Number:
JP1612091A
Publication Date:
September 10, 1992
Filing Date:
February 07, 1991
Export Citation:
Assignee:
SHARP KK
International Classes:
H03M1/08; H03M1/12; H04N19/00; H04N19/423; H04N19/85; (IPC1-7): H03M1/08; H03M1/12; H04N7/13
Attorney, Agent or Firm:
Nishikyo Keiichiro (1 outside)