PURPOSE: To prevent from accumulating processing due to the priority control of conversion request by permitting execution to the one with the highest order from among the holding conversion request and performing priority control by a hardware.

CONSTITUTION: When a flag Fl of conversion request (1) is set, this is detected by a highest order detection circuit 12, an A/D conversion request enable signal El is inputted to a gate circuit 101, and conversion request S1 is supplied to an A/D conversion control circuit 11. The A/D conversion control circuit 11 receiving this outputs a A/D conversion starting signal II, inputs a channel rewriting signal d1 to a channel storage part 81b, and inputs a writing starting signal IV and a register selection signal V to an R/W control circuit 6. Thus, the signal of the channel designated by the conversion request (1) from a multiplexer 2 to an A/D converter 3, and the A/D converter 3 converts the signal to a digital signal.