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Title:
A/D CONVERTER
Document Type and Number:
Japanese Patent JPH05268085
Kind Code:
A
Abstract:

PURPOSE: To provide a selecting device transmitting either of high order or low order bit of code of the calculation result of an accumulation adder and sending it to an information transmission line while selecting the high order bit when the absolute value at the RF level is required when transmission bit capacity (n) on the information transmission line is smaller than bit capacity (m) of the accumulation adder and selecting the low order bit when the fluctuation information on noise level is required.

CONSTITUTION: When a code 13 after accumulation addition added by the prescribed number by an accumulation adder 3 is taken as high-order bit (for example 8 bits) representing the average RF level and the low order bit (for example 5 bits) representing the noise fluctuation level, (m) is equal to 13. When transmission capacity of the code 14 on the information transmission line is (n)=8 bits, the transmission can be performed by only selecting either high-order or low order bit. A selecting device 4 selects the high-order or low order bit of the (m) bit at its transmission to the information transmission line.


Inventors:
Hiroki Hinohara
Application Number:
JP5869192A
Publication Date:
October 15, 1993
Filing Date:
March 17, 1992
Export Citation:
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Assignee:
NEC
International Classes:
H03M1/08; H03M1/12; H03M7/30; (IPC1-7): H03M1/12; H03M1/08; H03M7/30
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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