PURPOSE: To eliminate power loss at no signal by inputting a unipolar PWM signal where a front ridge of each pulse is synchronized with a clock of 50% duty factor, geneating a pulse consecutive between the pulse tail ridge and the midpoint of a clock period and outputting a pulse corresponding to a lead period in a pulse train while the phase is inverted.

CONSTITUTION: The PWM signal 1 and a CK' being the inverted clock CK2 are exclusively ORed at an exclusive OR circuit 5 and a signal E is obtained. The width of the signal E is equal to the interval between the trailing edge of each pulse of the PWM signal 1 and the midpoint (m) of the clock period. When the trailing edge of the PWM signal 1 is delayed from the midpoint of the clock period in the relation of the clock CK2, an output signal F of the polarity decision circuit 3 is logical "1" and when it is led, the signal F is logical "0", and when the signal F is logical "1", the switch S1 is thrown to the position + and when logical "0", the switch S1 is thrown to the position -. That is, when the trailing edge of the PWM signal is led from the midpoint of the clock period, a signal G is inverted by a polarity inverting circuit 7 and inputted to an amplifier 8, converted into a bipolar PWM signal and fed to a load 9.