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Patent Searching and Data


Title:
SERIAL/PARALLEL CONVERTING CIRCUIT WITH INDETERMINACY REMOVING FUNCTION
Document Type and Number:
Japanese Patent JPH06334537
Kind Code:
A
Abstract:

PURPOSE: To instantaneously rearrange a signal into the same data array with a parallel signal before parallel/serial conversion as to the serial/parallel converting circuit with the indeterminacy removing function.

CONSTITUTION: This circuit is equipped with a serial/parallel conversion part 1 which converts a parallel/serial-converted serial signal into a parallel signal, a parallel/serial conversion part 2 which converts the parallel signal converted by the serial/parallel conversion part 1 into a serial signal, a comparison and decision part 3 which compares the serial signal from the parallel/serial conversion part 2 with the serial signal inputted to the serial/parallel conversion part 1 and decides whether or not the conversion by the serial/parallel conversion part 1 is performed at specific timing, and a correction part 4 which corrects the parallel signal from the serial/parallel conversion part 1 on the basis of the comparison and decision result of the comparison and decision part 3 unless the conversion by the serial/parallel conversion part 1 is done at the specific timing.


Inventors:
YOSHIDA KATSUJI
Application Number:
JP11975993A
Publication Date:
December 02, 1994
Filing Date:
May 21, 1993
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H03L7/00; H03M9/00; H04L29/02; (IPC1-7): H03M9/00; H04L29/02
Attorney, Agent or Firm:
Yu Sanada