PURPOSE: To regenerate a large amplitude value with a small number of bits by limiting the number of bits of digital waveform data and controlling a data input period according to an amplitude level.

CONSTITUTION: The high-order two bits of data EV/AM inputted while its number of bits is limited are decoded by a decoder 298 and the remaining four bits are decoded by a decoder 300. Four output lines of the decoder 298 are connected to control inputs of gate elements GA1∼GA4 of four gate element groups G1∼G4 of an analog voltage generating circuit 302, and 16 output lines of the decoder 300 are connected to control inputs of 16 gate elements where voltage- division outputs of voltage dividing resistances are passed in the gate element groups G1∼G4 of the circuit 302. Power lines PS1 and PS2 of the circuit 302 are supplied with a voltage VH from a power circuit 304 and an intermediate voltage VC according to a control input TG/SG. Further, a pulse width control circuit 306 controls the pulse width of the output voltage of the circuit 302 according to clock signals 1 and 2 and the voltage output of the circuit 306 is amplified by an amplifier 308 to output a voltage VOUT.