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Title:
【発明の名称】くりこみインタリーバおよびインタリーブ解除器
Document Type and Number:
Japanese Patent JP3169613
Kind Code:
B2
Abstract:
A convolutional interleaver or deinterleaver comprises an address signal generator for repeatedly generating [(B-1)N/2]+1 sequences of address signals, where B is a desired interleave depth and N is a value equal to or greater than the number of data bytes in a R-S block of the data stream. Each of the sequences corresponds to a respective row of a B column matrix, the first column of which comprises [(B-1)N/2]+1 consecutively numbered values. Each remaining column comprises the preceding column rotated by an integer multiple of N/B. The address signals are applied to a memory having [(B-1)N/2]+1 storage locations for reading the data stored at the address memory location and then writing the current data byte to the same memory location.

Inventors:
Fimov, mark
Harozan, Scott F.
Housey, Raymond Sea.
Application Number:
JP51811495A
Publication Date:
May 28, 2001
Filing Date:
December 15, 1994
Export Citation:
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Assignee:
Zenith, Electronics Corporation
International Classes:
H03M13/27; H04L27/00; H04N19/89; (IPC1-7): H03M13/27; H04L27/00; H04N7/24
Domestic Patent References:
JP370318A
JP5234265A
JP5234259A
Attorney, Agent or Firm:
Kazuo Sato (3 others)