Title:
畳み込み演算回路
Document Type and Number:
Japanese Patent JP4630056
Kind Code:
B2
Abstract:
There is provided a convolution operation circuit that performs a convolution operation on a provided digital signal. The convolution operation circuit includes a data dividing section that generates a plurality of divided data obtained by dividing respective amplitude data of the digital signal into a plurality of bit areas, an arithmetic section that performs a predetermined convolution operation on the respective divided data of the respective amplitude data in a time-sharing mode and outputs the result, and a coupling section that couples the divided data output from the arithmetic section for each of the amplitude data.
Inventors:
Tsuyoshi Takahashi
Application Number:
JP2004374928A
Publication Date:
February 09, 2011
Filing Date:
December 24, 2004
Export Citation:
Assignee:
Advantest Corporation
International Classes:
H03H17/06
Domestic Patent References:
| JP2002217787A | ||||
| JP6224695A | ||||
| JP6350396A | ||||
| JP7038381A | ||||
| JP11312953A | ||||
| JP2003133911A |
Attorney, Agent or Firm:
Akihiro Ryuka