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Title:
レートマッチングによる計算効率の高い畳み込み符号化
Document Type and Number:
Japanese Patent JP5379127
Kind Code:
B2
Abstract:
An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate.

Inventors:
Chen, Yun Hu
Application Number:
JP2010510902A
Publication Date:
December 25, 2013
Filing Date:
June 06, 2008
Export Citation:
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Assignee:
Telefon Akti Bora Get Elm Ericson (Pubble)
International Classes:
H03M13/23; H03M13/27; H04B14/04; H04L1/00
Domestic Patent References:
JP2005073266A
JP2002526966A
JP2004535694A
JP2006303906A
JP2005514848A
JP2008526134A
Foreign References:
WO2006069392A1
Other References:
Motorola,Convolutional code rate matching in LTE,3GPP TSG-RAN WG1#48b R1-071324,2007年 3月26日,URL,http://www.3gpp.org/ftp/tsg_ran/WG1_RL1/TSGR1_48b/Docs/R1-071324.zip
Philips,Text Proposal for Spatial Temporal Turbo Channel Coding (STTCC),3GPP R1-050723,2005年 9月 2日
ZTE,Rate matching improvement for turbo coding,3GPP R1-072101,2007年 5月11日
Samsung,Bit interleaving to resolve Turbo coder irregularities in HSDPA,3GPP R1-030808,2003年 8月29日
Jung-Fu Cheng et al.,Analysis of Circular Buffer Rate Matching for LTE Turbo Code,Vehicular Technology Conference, 2008. VTC 2008-Fall. IEEE 68th ,2008年 9月24日,pp.1-5
Attorney, Agent or Firm:
Miaki Kametani
Tetsuo Kanamoto
Koji Hagiwara
Kazuki Matsumoto