Title:
コプロセッサ・データ・アクセス制御
Document Type and Number:
Japanese Patent JP3681407
Kind Code:
B2
Abstract:
A digital signal processing system comprising a central processing unit core 2, a memory 8 and a coprocessor 4 operates using coprocessor memory access instructions (e.g. LDC, STC). The addressing mode information within these coprocessor memory access instructions (P, U, W, Offset) not only controls the addressing mode used by the central processing unit core 2 but is also used by the coprocessor 4 to determine the number of data words in the transfer being specified such that the coprocessor 4 can terminate the transfer at the appropriate time. Knowledge in advance of the number of words in a transfer is also advantageous in some bus systems, such as those that can be used with synchronous DRAM. The Offset field within the instruction may be used to specify changes to be made in the value provided by the central processing unit core 2 upon execution of a particular instruction and also to specify the number of words in the transfer. This arrangement is well suited to working through a regular array of data such as in digital signal processing operations. If the Offset field is not being used, then the number of words to be transferred may default to 1.
Inventors:
York, richard
Seal, David, James
Sims, dominic
Seal, David, James
Sims, dominic
Application Number:
JP50180699A
Publication Date:
August 10, 2005
Filing Date:
January 12, 1998
Export Citation:
Assignee:
RM Limited
International Classes:
G06F9/30; G06F9/312; G06F15/16; G06F9/32; G06F9/355; G06F9/38; (IPC1-7): G06F9/30; G06F9/38
Domestic Patent References:
| JP916398A | ||||
| JP358228A | ||||
| JP6355638A |
Attorney, Agent or Firm:
Hideto Asamura
Hajime Asamura
Hayashi Zouzo
Kuniaki Shimizu
Hajime Asamura
Hayashi Zouzo
Kuniaki Shimizu
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