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Patent Searching and Data


Title:
CORRECTING METHOD FOR TESTING INSTRUCTION
Document Type and Number:
Japanese Patent JPH06324904
Kind Code:
A
Abstract:

PURPOSE: To suppress the reduction of test accuracy at a minimum concerning the correcting method for testing instruction on a method for testing an information processor based on the executed results of successively generated testing instruction sequences.

CONSTITUTION: The combination of the conditions of instruction operands to disable the execution of the objective instruction among executing conditions related to the instruction operands including register interference relation with the preceding instruction based on executed result data such as an error list, for example, concerning generated optional testing instruction is defined as an instruction inhibit parameter table (2) to be referred to by a testing instruction correction processing part (program) 12, and the testing instruction correction processing part 12 performs correction so as to erase the conditions instructed by the instruction inhibit condition parameter table (2) concerning various values to be provided for the instruction operand while referring to the table (2), for which the inhibit conditions concerning the execution are composed of parameters, of the instruction operand to be the target of correction.


Inventors:
KOBAYASHI YUKIO
Application Number:
JP11509593A
Publication Date:
November 25, 1994
Filing Date:
May 18, 1993
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F11/22; (IPC1-7): G06F11/22
Attorney, Agent or Firm:
Teiichi