PURPOSE: To facilitate high-level processing by a simple clock by allowing a major analog shift register to add and transfer its operation output.

CONSTITUTION: While an analog input is circulated in the analog shift register as a minor loop 3W7, e.g. CCD, the correlative value of each bit delay is found through a differential absolute value circuit 8 and outputted to an output terminal 10 through an analog shift register 9. Firstly, a reset terminal 11 is decreased from a high to a low level to release a ten frequency divider 12, RS- FF (RS-flip-flop) 13, and ten frequency divider 14 from being reset and while a clock is supplied to a terminal 15, information to be correlated is applied to terminals 1 and 2.