To provide a correlator which satisfies both the improvement of arithmetic precision and the reduction of power consumption at the same time even when a fast operation speed is required for a prolonged binary code system.

In a correlator 1, switched capacitor type analog signal integrators 11a and 11b are cascade-connected. The analog signal integrator in the first stage operates sampling of an analog input voltage Vin in a prescribed cycle, determines the code of a sampling value based on a binary code system, and integrates and outputs each sampling value. The analog signal integrator 11b in the next stage operates sampling of the input voltage in the reset cycle of the analog signal integrator 11a in the previous stage, and integrates and outputs the sampling value. Thus, even when the system length is long, the gain of each analog signal integrator 11a and 11b can remain relatively large, and saturation of the correlator 1 can be prevented.