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Title:
COUNT VALUE MONITOR CIRCUIT
Document Type and Number:
Japanese Patent JPH04207418
Kind Code:
A
Abstract:

PURPOSE: To prevent noise from being given to the monitor circuit by connecting a D terminal of a D flip-flop in the inside of a synchronous counter to an input terminal of a comparator and providing other D flip-flop receiving an output signal of the comparator and a clock signal to the monitor circuit.

CONSTITUTION: A D terminal of a D flip-flop in the inside of a synchronous counter 1 is connected to an input terminal of a comparator 4 so that the comparator 4 outputs a coincidence signal earlier by one clock signal than a time when a count data and a data set to a register 3 are coincident. Then the monitor circuit is provided with other D flip-flop 12 so that a trigger is given to the flip-flop with a delay by one clock signal from a time when the coincidence signal is outputted. Thus, malfunction of the flip-flop 5 due to noise such as spike outputted from the comparator 4 is avoided.


Inventors:
AKIMOTO CHIEKO
Application Number:
JP33048390A
Publication Date:
July 29, 1992
Filing Date:
November 30, 1990
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H03K21/40; (IPC1-7): H03K21/40
Attorney, Agent or Firm:
Mitsuteru Soga (5 people outside)



 
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