Title:
COUNTER CELL AND COUNTER CIRCUIT
Document Type and Number:
Japanese Patent JPH07202682
Kind Code:
A
Abstract:
PURPOSE: To form each bit cell by comparatively small number of elements on plural identical stages. CONSTITUTION: A counter cell includes a latch circuit, a control circuit and a pull-up circuit. The latch circuit is formed by a 1st clock-operated half latch 32, a 2nd clock-operated half latch 34 and an inverer INV1 for storing a binary output signal. The half latch 32 transfers a binary output signal from its input to its output in response to a 1st clock phase signal. The half latch 34 transfers a binary output signal from its input to its output in response to a 2nd clock phase signal. A control circuit selectively sends the 1st clock phase signal to the half latch 32 so as to allow to toggle the state of the binary output signal in response to an input complement signal. A pull-up circuit generates an output complement signal.
Inventors:
PURANEE GIYAGURANI
Application Number:
JP7714892A
Publication Date:
August 04, 1995
Filing Date:
March 31, 1992
Export Citation:
Assignee:
ADVANCED MICRO DEVICES INC
International Classes:
H03K3/037; H03K3/356; H03K23/44; H03K23/00; H03K23/60; (IPC1-7): H03K23/00; H03K23/60
Attorney, Agent or Firm:
Hisami Fukami (4 outside)