To prevent timing of output signals from being deviated in a synchronous type counter circuit by taking layout into account.

A counter circuit outputs count values Q0-Q15 of MN bits using M (e.g., four) pieces of N-bit (e.g., 4-bit) synchronous counters BLK1-BLK4 and comprises a coincidence detection circuit 30 which outputs a coincidence detection signal DET when the count value becomes a predetermined value of S0-S15. In such a counter circuit, the M pieces of N-bit synchronous counters BLK1-BLK4 are adjacently disposed in parallel and the coincidence detection circuit 30 is disposed adjacently to terminal portions of these N-bit synchronous counters BLK1-BLK4 disposed in parallel.