To save power of a clock circuit unit for controlling a DLL (Delay Locked Loop) circuit etc. which requires a start-up time before normal operation.
A clock generating circuit is connected to a counter circuit which controls an operation timing of the DLL circuit etc. and gives a clock signal intermittently to the counter circuit from the clock generating circuit, so that the clock circuit intermittently operates and the power-saving is attained. In this case, the operation of the counter circuit may be stopped by giving an output of the counter circuit to the clock generating circuit, or a determination circuit for determining a specific status, e.g. Slow Precharge Power Down state may be connected to the clock generating circuit, to control the clock generating circuit by referring to the determination result of the determination circuit.
FUJISAWA HIROKI
| JP2000021165A | 2000-01-21 | |||
| JP2005228426A | 2005-08-25 | |||
| JP2000021165A | 2000-01-21 |
Shuichi Fukuda
Takashi Sasaki
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