To provide a counter circuit operating at a desired phase independently of an initial state such as in power rising.

A reset pulse generating circuit (3) performs decoding when a counter output (SB1) is a prescribed value Y-a and outputs a reset pulse (SDc) in a timing when the counter output (SB1) reaches Y after a-clocks, a first selection circuit (12) delays an external load pulse (Sc) by (b)-clocks to generate a delayed external load pulse (Scd) and to select an external load pulse when the external load pulse (Sc) is effective or selects the delayed external load pulse when the delayed external load pulse (ScD) is effective, and a second selection circuit (13) selects a first load value X when the external load pulse is selected or selects a second load value X+b when the delayed external load pulse is selected.