To provide a counter circuit capable of preventing count data from being erased by holding the count data until it is read from a register after the count data is stored in the register from the counter circuit.
This counter circuit is provided with a first counter 22 in which a first load signal is supplied, the initial value is loaded and inputted pulse signals are counted, an adder 24 in which the count data of the first counter 22 is added to the value of the inputted pulse signals and a second counter 26 in which a second load signal different in timing from the first load signal is supplied, the output value of the adder 24 is loaded as the initial value and the pulse signals are counted. Thus, the same count data as the register is held in the second counter 26 until the initial value is loaded on the second counter 26 after the initial value is loaded on the first counter 22, thereby preventing the count data from being erased.
Takeda, Hirotoshi
Kuwabara, Takashi
Nakayama, Yoshiteru
