To solve a problem that in a binary counter, counter operation by a rapid clock is unstable as affected by a delay time caused by operation, thus requiring a large-sized circuit in a shift counter for obtaining a large count value.

A plurality of shift registers 1 to 4 are provided. Passage of count up enable is blocked by a logical product gate 10 by using a value of an uppermost bit of the shift register 1 of the forefront stage as a shift operation enable signal and only at the time of enable, and count up enable is input to a shift register of the next stage. Consequently, since a shift counter of each stage shows each digit of a count value, circuit scale is reduced. Furthermore, since each shift counter just shifts a value in a shift register, a delay time does not matter and rapid operation can be ensured stably.