To provide a counter circuit capable of forming a plurality of pulse signals of different periods, without increasing the circuit scale.

The counter circuit comprises an initial value register single port RAM 5, having initial value registers 50 allotted for storing N initial values; a counter register single port RAM 6 having N counter registers 60 disposed therefor; and a control circuit 7 for executing counter processes for counters. The control circuit 7 repeatedly executes each counter process in a time division manner, using an arithmetic circuit 70.