To provide a counter circuit where jitters are equivalent to those of a synchronous type counter, the counter circuit making it possible to change the pulse width of the output wave of an output signal.

The counter circuit comprises: shift registers 111 to 1110 which generate frequency division setting data DB; shift registers 11 to 110 which generate data DC for determining the pulse width of a signal COUT; a register unit which loads the data DB when a signal LS is input and counts down based on the data; a first signal creation unit which outputs a signal LS when the down-count value reaches a specified value; an output creation circuit 3 which, when outputting a signal COUT, begins a pulse of the signal COUT with the same timing as the signal LS is output; and a comparison circuit 2 which outputs a pulse signal when a period from the time a count value QD reaches a specified value till the time the current value QD is acquired, as found by comparison between data DC and a count value QD, corresponds to a predetermined pulse width. The output creation circuit 3 terminates the pulse of the output signal COUT when a change in the pulse signal is detected.