To provide a counter circuit that can correct a malfunction of the counter circuit in a simple configuration.
The counter circuit for counting a predetermined time includes: a pair of data holding circuits FF1, FF2 for receiving and holding the same data on the basis of the same clock; logic circuits OR0, OR1, ORn for receiving plural pieces of data held in the pair of data holding circuits FF1, FF2, and if both of the plural pieces of data are logically the same, outputting data depending on the logic of the plural pieces of data and, if one of the plural pieces of data is logically first logic and the other is logically second logic, outputting data depending on the data input of the first logic; and an arithmetic circuit 11 for performing an increment operation of outputs of the logic circuits OR0, OR1, ORn and outputting the result of operation to each of the pair of data holding circuits.
| JPS5363968 | ELECTRONIC COUNTER |
| JPH10107619A | 1998-04-24 | |||
| JPH06237151A | 1994-08-23 | |||
| JP2003258628A | 2003-09-12 | |||
| JP2010114581A | 2010-05-20 | |||
| JP2004336123A | 2004-11-25 | |||
| JPH1056369A | 1998-02-24 | |||
| JPH10107619A | 1998-04-24 | |||
| JPH06237151A | 1994-08-23 | |||
| JP2003258628A | 2003-09-12 | |||
| JP2010114581A | 2010-05-20 | |||
| JP2004336123A | 2004-11-25 | |||
| JPH1056369A | 1998-02-24 |
Koichi Itsubo
Higuchi Souji
Ryu Kobayashi
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