Title:
COUNTER CIRCUIT
Document Type and Number:
Japanese Patent JP3338294
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce the number of times of operations of a flip-flop for constituting the counter of a low-order bit and to reduce power consumption by stopping the count operation of the counter of a low-order bit group when the counter of a high-order bit group performs counting.
SOLUTION: A frequency divider 101 inputs the original clock signals (f) and outputs the frequency divided signals f/2k of the frequency of 1/2k of the original clock frequency and the frequency divided signals f/2m of the frequency of 1/2m of the original clock frequency. Then, until high-order bit data held in a register 107 and output match, the frequency divided signals f/2m are supplied only to a high-order bit counter group 106. Then, similarly, until low-order bit data held in the register 107 and the output match finally, the original clocks signals (f) are supplied only to a low-order bit counter group 104 successively. In such a manner, during the operation of a certain counter, the operation of the other counter is stopped.
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Inventors:
Seiichi Tomita
Kazuhiko Ohashi
Kazuhiko Ohashi
Application Number:
JP18071796A
Publication Date:
October 28, 2002
Filing Date:
July 10, 1996
Export Citation:
Assignee:
Toshiba Microelectronics Corporation
Toshiba Corporation
Toshiba Corporation
International Classes:
H03K21/00; (IPC1-7): H03K21/00
Domestic Patent References:
| JP59208945A | ||||
| JP7248741A | ||||
| JP6204873A | ||||
| JP63166318A |
Attorney, Agent or Firm:
Takehiko Suzue (6 outside)