Title:
COUNTER CIRCUIT
Document Type and Number:
Japanese Patent JP3711455
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a high-speed multi-bit binary counter circuit.
SOLUTION: In a multi-bit counter circuit in which 1-bit counter circuits 1 are coupled in series, the 1-bit counter circuits 1 are separated into at least one lower order 1-bit counter 1 taking charge of lower order bit outputs and a plurality of upper order 1-bit counters 1 taking charge of upper bit outputs. Output signals from the upper order 1-bit counters 1 are output via latch circuits 3, and a signal CLK 2 generated by using a signal generating circuit 2 to which the final stage output from the lower order 1-bit counter circuits 1 is input to the upper order 1-bit counters 1 as the first stage input signal. The latch circuits 3 are controlled timely by the signal CLK 2.
Inventors:
Mitsuhiro Yamamura
Application Number:
JP2003068348A
Publication Date:
November 02, 2005
Filing Date:
March 13, 2003
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
H03K5/00; H03K23/42; (IPC1-7): H03K23/42; H03K5/00
Domestic Patent References:
| JP2000174614A | ||||
| JP7212223A |
Attorney, Agent or Firm:
Masahiko Ueyanagi
Fujitsuna Hideyoshi
Osamu Suzawa
Fujitsuna Hideyoshi
Osamu Suzawa