PURPOSE: To obtain an exact count value without any influence to the duty factor or speed of a clock for timing in order to count an input pulse by holding a preceding dividing output when the input pulse is an L.

CONSTITUTION: For a dividing means 10, a clock CLK of a prescribed speed is directly connected to the clock terminal and when an input pulse 1 of the H is inputted to a pulse input control means 20, the input pulse 1 is through sent to the data terminal of the dividing means 10 by the pulse input control means 20 and successively divided with the timing of the clock CLK. On the other hand, when the input pulse 1 of an L is inputted to the pulse input control means 20, the pulse input control means 20 holds the output of the dividing means 10 only by a bit number to correspond to the L according to the logical condition of a specified pattern pulse from a pulse pattern converting means 30 and the inverting output of the dividing means 10. Thus, regardless of the fluctuation and the speed of the duty factor of the clock, which goes to be a timing signal when the input pulse is counted, the input pulse can be counted highly speedily and exactly.