PURPOSE: To decrease number of D-FFs and to reduce the circuit scale and power consumption by feeding back an inverting reversed phase output of a final stage D-FF to an input of a 1st stage D-FF.

CONSTITUTION: A reversed phase output Q4 (5f) of a final stage D-FF (1) is fed back to an input of a 1st stage D-FF to bring an output Q1 (5a) of the 1st stage D-FF goes to a level L by an input of a succeeding 5th clock pulse (4). Thus, a pulse of a four-clock length is generated for each four-clock at outputs Q1-Q4 (5a-5d) of each D-FF (1) and the phase is shifted sequentially by one clock each at the outputs Q1-Q4 (5a-5d). The outputs Q1 (5a) and Q4 (5d) are ANDed by using the pulses and an output pulse (6) with one clock length whose level goes to H for each eight-clock is obtained.