PURPOSE: To prevent the malfunction of this counter circuit by providing 2-stages of delay flip-flops generating a pulse to load an n-bit counter to the counter circuit so as to make the holding time of the counter sufficient.

CONSTITUTION: When a clock signal 4 is inputted to a control 1 and the counted value reaches all '1', a carry-out 5 goes to '1' as an output. Then the output pulse of the carry-out 5 is given to a flip-flop 2, the input is delayed at a leading edge of the clock signal 4 and a QC output 6 is outputted. Then the outputted QC output 6 is given to a 2nd delay flip-flop 3 and the QC output 6 is delayed by the leading edge of the clock signal 4. The flip-flop 3 outputs a QC output 7 rising with a delay of a half period of the clock signal 4 from the leading edge of the clock signal 4 and the QC output 7 is inputted to a LOAD terminal of the counter 1. Thus, the hold time of the counter is sufficiently taken, thereby preventing the malfunction.