PURPOSE: To operate even by a high speed clock by inputting a counter pulse signal synchronously with the clock of the precharge signal of a carry generating circuit.
CONSTITUTION: This circuit is equipped with latch circuits 1 and 3 for storing a count value, and a selected-circuit which selects whether the initial data of a counter are inputted or the count value of currents is inputted from a data bus 10 to the latch circuit 1 by a preset signal PRS. And also, this circuit is equipped with a carry generating circuit 5 in which both a count pulse CNTP and the output of the latch circuit 1 are constituted by the logic of a dynamic NAND, and a logical arithmetic circuit 2 which operates the logical arithmetic operation of the output of the carry generating circuit 5 and the output of the latch circuit 1. Then, a count signal is inputted as the input signal of the precharge circuit of the carry generating circuit 5. Thus, a carry signal is turned to be available at the same time the count pulse signal is turned into 'High', and this circuit can stably be operated even by the high speed clock.
YASUDA SADAHIRO
JP60129747B | ||||
JPH03247118A | 1991-11-05 |