PURPOSE: To suppress the increase in a circuit scale due to the increase in a bit number of an m-any binary counter, to prevent the appearance of a non- definition state to the output of the m-ary binary counter with simple circuit configuration and to make the counter output stable.

CONSTITUTION: When an input clock CP is imparted to the m-ary binary counter 60 with a reset as a pulse input CPS via an AND 50, the counter 60 counts the CPS and gives a carry signal MOV to a delay circuit 80 in a clock control circuit 70. The delay circuit 80 delays the MOV by the prescribed number (k) of the CP. A OR 90 selects either the MOV or the output of the delay circuit by using mode switching signal SEL and sends a clock control signal EN to the AND 50. The AND 50 implements input the permission or the inhibition of the CP to/from counter 60. Thus, the SEL is used to switch either the m-ary or the (m+k)-ary.