PURPOSE: To change the frequency division ratio in a wide range with a small amount of hardware and to obtain a counter circuit capable of counting many pulses by properly using a count register consisting of plural bits for a frequency divider part and the counter part.

CONSTITUTION: A counter register 11 is provided where one-bit circuits each of which outputs a carry signal at the time of the occurrence of the state change due to application of a clock 4 are cascaded. A control circuit 14 is provided to operate prescribed lower bits and the other upper bits of the counter register 11 as a frequency divider part 12 and a counter part 13 respectively. Thus, the n-bit count register is used as the frequency divider 12 and the counter 13 to set the frequency division ratio in a wide range, and the counter circuit is obtained where the count error due to count switching is fixed.