PURPOSE: To reduce the circuit scale with respect to the counter circuit counting up or down the prescribed number for each input of one clock especially.

CONSTITUTION: An OR circuit 22 ORs 1st and 2nd enable signals EN1, EN2 to generate a new enable signal. Furthermore, enable signals EN1, EN2 are ANDed by an AND circuit 25 to generate a control signal. A new enable signal is inputted to AND circuits 28, 30, 32 to vary outputs of flip-flops 212-214. Furthermore, the control signal is inputted to an exclusive OR 261 provided to the input side of the flip-flop 211 outputting a bit value Q1 of the least significant digit in 4-bit counts by the control signals Q1-Q4 to fix the bit value Q1. Thus, the count is increased by '2' each by each one clock input.