PURPOSE: To provide an UP/DOWN counter circuit capable of operating normally counting even when an up clock input and a down clock input are duplicated timewise.

CONSTITUTION: A storage circuit 1 fetches the output of a selector 2 by the output E of an OR circuit 10 and gives a parallel output to +1, -1 circuits 3, 4. The circuits 3, 4 respectively increment/decrement it by 1. The selector 2 selectively outputs the output of the +1 (-1) circuit 3 (4) at A='1' ('0'). An UP/DOWN detection circuit 7 detects the front edge of an UP clock 5 (DOWN clock 6) to set the level of lines A, B to '1' and detects a tail end edge to set the level of the lines A, B to '0' after the lapse of a prescribed time. When an input condition is established, AND circuits 8, 9 output a pulse with a width equivalent to the prescribed time. When the clocks 5, 6 timewise take place overlappingly, for example, when the line B goes to '1' while the line A is set to '1,' since no change is caused in the counting by one increment/ one decrement, the lines A, B are quickly set to '0,' and when any of the lines A, B is set to '1' and goes regularly to '0,' an output is obtained at one of the circuits 8, 9, the output E of a circuit 10 is generated, the counter is implemented and the circuit 7 transits to succeeding detection operation.