PURPOSE: To prevent the deviation of counting in the counter circuit when the clock changes slower than data.

CONSTITUTION: A latch circuit L6 in the final stage and a dummy latch circuit L0 changing in phase are added on the front of a latch circuit L1 at the first stage of the counter circuit whose cycle is determined by a latch circuit and the number of inverters. An inverter I0 making the clock is added. Thus, the deviation of counting of the counter due to the delay of data can be prevented by adding the latch circuit L0 and the inverter I0.