PURPOSE: To obtain a circuit capable of executing rapid operation and having a small chip area by combining a synchronous counter and an asynchronous counter.

CONSTITUTION: Each of D flip flops(FFs) 1, 4 generates an output signal at the timing of a clock signal and a counter function is attained by a logic circuit consisting of a multiplexer 2 and an inverter 3. Counter operation having more bits is attained by passing the output signal of the D-FF 4 through T-FFs 5, 6. When a synchronous counter is used for a part requiring rapid operation in the counter constitution, the circuit can correspond to rapid operation. The number of asynchronous counters to be connected to succeeding stages can be increased until the increment exerts influence upon the rapid operation, so that the area of the circuit can be reduced as compared with a counter circuit constituted of only synchronous counters.