To provide a counter circuit with which a correct counter value can be read out, without stopping a counter and high-speed processing is enabled.

Each time a counter clock CLK is inputted, the counter value of counter is updated. Each flip-flop for a latch latches the output of counter at the fore edge or rear edge of read signal. All the outputs of flip-flop for latch or one part of them is inputted to a selector circuit. The outputs of all the flip-flops for the latch are inputted to a comparator circuit, and the comparator circuit compares the inputted output values of flip-flops for the latch, selects one output of a flip-flop for latch by majority and sends a select signal showing the selected output of the flip-flop for the latch to the selector circuit. Based on the value of the select signal, the selector circuit selects one piece of input data and outputs the selected input data.