PURPOSE: To expand a parity predicting circuit and to reduce a titled counter circuit requiring a parity check in size and weight by constituting the parity predicting circuit by read-only memories.

CONSTITUTION: A counter 10 inputs a clock and an initializing signal through input lines 203, 204 and sends a counter output of 16 bits through output lines 101∼116. The read-only memories 41, 42 act as a parity predicting circuit and the output of the memory 42 is used as a parity predicting bit and inputted to a gate 62. The gate 62 constitutes an expecting parity storing circuit together with an expecting parity flip-flop (FF) 61. A parity check circuit 30 compares an expecting parity bit stored in the FF61 with a parity bit corresponding to the output of the counter 10 and detects an error.