PURPOSE: To obtain stably a count output in synchronizing with an input signal by preventing a mis-trigger signal produced between a ripple carry signal being an overflow signal of a counter and an input drive signal.

CONSTITUTION: A rectangular wave inputted from an input 13 is converted into a drive pulse signal having a minimum pulse width enabling to start 4-bit synchronous binary counters 2∼5 of 4-stage cascade connecting constitution. This signal is fed to multi-input AND circuits 9∼12. The AND circuit 9 corrects a time delay of a signal propagated through other AND circuits. The output pulse of the circuit 9 starts the counter 2 of the 1st stage. In this case, the ripple carry signal is outputted at the count of the drive pulse of the n-th time, delayed by a delay circuit 6, fed to an AND circuit 10, and when the (n+1)-th signal is generated, the circuit 10 outputs a signal, which is inputted to the counter 3 which outputs a signal in synchronizing with the counter 2.