PURPOSE: To easily increase a quantity of information representing relative relation, by controlling a counter by using a control pulse which represents the difference of first and second timing signals on a time base.
CONSTITUTION: A deciding device 101 decides the temporal lead or lag of the second timing signal 2 for the first timing signal, and outputs a decision result 5. A comparator 102 compares the position relation of the first timing signal 1 and the second timing signal 2 on the time base, and shows the difference between them on the time base, and also, outputs the control pulse 7 to control the counter 3. The counter 3 counts a time difference between the first timing signal 1 and the second timing signal 2 in the bit unit of a clock 3 under the control of the control pulse, and outputs the difference of the bit unit of two timing signals on the time base as bit information 6-1(LSB)∼6-8(MSB). In such a way, it is possible to obtain a counter circuit with flexibility for the correspondence of a counting range and realizable in easy simple constitution.
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JPS5714434U | 1982-01-25 | |||
JPS5997069A | 1984-06-04 | |||
JPS53117467A | 1978-10-13 | |||
JPS5296563A | 1977-08-13 | |||
JPS58171131A | 1983-10-07 |