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Title:
COUNTER CIRCUIT
Document Type and Number:
Japanese Patent JPS6446317
Kind Code:
A
Abstract:

PURPOSE: To easily increase a quantity of information representing relative relation, by controlling a counter by using a control pulse which represents the difference of first and second timing signals on a time base.

CONSTITUTION: A deciding device 101 decides the temporal lead or lag of the second timing signal 2 for the first timing signal, and outputs a decision result 5. A comparator 102 compares the position relation of the first timing signal 1 and the second timing signal 2 on the time base, and shows the difference between them on the time base, and also, outputs the control pulse 7 to control the counter 3. The counter 3 counts a time difference between the first timing signal 1 and the second timing signal 2 in the bit unit of a clock 3 under the control of the control pulse, and outputs the difference of the bit unit of two timing signals on the time base as bit information 6-1(LSB)∼6-8(MSB). In such a way, it is possible to obtain a counter circuit with flexibility for the correspondence of a counting range and realizable in easy simple constitution.


Inventors:
OOTAWA MASAYUKI
Application Number:
JP20174587A
Publication Date:
February 20, 1989
Filing Date:
August 14, 1987
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03K23/00; (IPC1-7): H03K23/00
Domestic Patent References:
JPS57203320A1982-12-13
JPS5714434U1982-01-25
JPS5997069A1984-06-04
JPS53117467A1978-10-13
JPS5296563A1977-08-13
JPS58171131A1983-10-07
Attorney, Agent or Firm:
Kihei Watanabe



 
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