PURPOSE: To continue the operation by inhibiting loading of an initial value to a counter by a self-loading signal when an external synchronizing signal generates a bit slip on a time base, and loading the initial value by only the external synchronizing signal.

CONSTITUTION: In the case an external synchronizing signal SYNC is subjected to bit slip in the direction being earlier by one clock on a time base, a generation timing of the signal SYNC, and a timing generated by a coincidence signal COI coincide with each other. In such a state, when a clock signal CLK is generated, an initial value is loaded to a counter 11 by the signal SYNC. However, as for an FF 12b, even if the signal CLK is generated, its setting is inhibited and generation of a self-loading signal SLD is obstructed by a self-loading signal generation obstructing part 12c. As a result, whenever the signal CLK is generated thereafter, counting from the initial value to a prescribed value is executed correctly. That is, at the time of generating the bit slip, a count value by the counter 11 is dissipated, but counting from the initial value to the prescribed value is repeated correctly.